• EPM7128SLC84-7 84-LCC(J-Lead)
EPM7128SLC84-7 84-LCC(J-Lead)

EPM7128SLC84-7

84-Pin PLCC Tube

在庫:6,612

  • 90日間のアフター保証
  • 365日の品質保証
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概要 EPM7128SLC84-7

The Intel MAX 7000S EPM7T128SLC84-7 is a Complex Programmable Logic Device (CPLD) that offers an efficient and cost-effective solution for system design and development. This 128-Macrocell, in-system programmable CPLD is designed to provide high-performance, low-power consumption, and reliability. With its 25,000 gates and 68 I/O pins, the EPM7T128SLC84-7 can be used in a wide range of applications including digital signal processing, data encryption, and telecommunications. The device operates from a power supply voltage of 4.75V to 5.25V and has an operating temperature range of 0°C to 70°C. Its small 84-LCC package makes it suitable for space-constrained designs. The EPM7T128SLC84-7 is ideal for applications that require high-speed, low-power consumption, and flexibility.

EPM7128SLC84-7

主な特長

  • additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.
  • In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.
  • Features...
  • High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
  • 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
  • – ISP circuitry compatible with IEEE Std. 1532
  • Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
  • Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
  • Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
  • 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
  • PCI-compliant devices available
  • Open-drain output option in MAX 7000S devices
  • Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
  • Programmable power-saving mode for a reduction of over 50% in each macrocell
  • Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
  • 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
  • Programmable security bit for protection of proprietary designs
  • 3.3-V or 5.0-V operation
  • – MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
  • – Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
  • Enhanced features available in MAX 7000E and MAX 7000S devices
  • – Six pin- or logic-driven output enable signals
  • – Two global clock signals with optional inversion
  • – Enhanced interconnect resources for improved routability
  • – Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
  • – Programmable output slew-rate control
  • Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations
  • Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
  • Programming support
  • – Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices
  • – The BitBlaster™ serial download cable, ByteBlasterMV™ parallel port download cable, and MasterBlaster™ serial/universal serial bus (USB) download cable program MAX 7000S devices

応用

  • Digital signal processing and conditioning
  • Data encryption and decryption systems
  • Telecommunications equipment and network devices
  • Automotive systems and control units
  • Industrial automation and control systems

仕様

以下は、選択された部品の特性やカテゴリーに関する基本的なパラメータである。

Series MAX® 7000S Package Tube
Product Status Obsolete Programmabe Verified
Programmable Type In System Programmable Delay Time tpd(1) Max 7.5 ns
Voltage Supply - Internal 4.75V ~ 5.25V Number of Logic Elements/Blocks 8
Number of Macrocells 128 Number of Gates 2500
Number of I/O 68 Operating Temperature 0°C ~ 70°C (TA)
Mounting Type Surface Mount Package / Case 84-LCC (J-Lead)
Supplier Device Package 84-PLCC (29.31x29.31) Base Product Number EPM7128

保証と返品

保証、返品、および追加情報

  • QAと返品ポリシー ?

    部品の品質保証: 365 日

    返品・返金:90日以内

    返品・交換:90日以内

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EPM7128SLC84-7

84-Pin PLCC Tube

在庫:

6,612