ISPLSI1032E-70LT

主な特長

• HIGH DENSITY PROGRAMMABLE LOGIC
• — 6000 PLD Gates
• — 64 I/O Pins, Eight Dedicated Inputs
• — 192 Registers
• — High Speed Global Interconnect
• — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
• — Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
• — fmax = 125 MHz Maximum Operating Frequency
• — tpd = 7.5 ns Propagation Delay
• — TTL Compatible Inputs and Outputs
• — Electrically Erasable and Reprogrammable
• — Non-Volatile
• — 100% Tested at Time of Manufacture
• — Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
• — In-System Programmable (ISP™) 5-Volt Only
• — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality
• — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
• — Complete Programmable Device Can Combine Glue Logic and Structured Designs
• — Enhanced Pin Locking Capability
• — Four Dedicated Clock Input Pins
• — Synchronous and Asynchronous Clocks
• — Programmable Output Slew Rate Control to Minimize Switching Noise
• — Flexible Pin Placement
• — Optimized Global Routing Pool Provides Global Interconnectivity
• ispLSI DEVELOPMENT TOOLS
• ispVHDL™ Systems
• — VHDL/Verilog-HDL/Schematic Design Options
• — Functional/Timing/VHDL Simulation Options ispDS™ Software
• — Lattice HDL or Boolean Logic Entry
• — Functional Simulator and Waveform Viewer
• ispDS+™ HDL Synthesis-Optimized Logic Fitter
• — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation
• — Static Timing Analyzer
• ISP Daisy Chain Download Software