• CY37064P100-125AXI 100-LQFP
  • CY37064P100-125AXI 100-LQFP
  • CY37064P100-125AXI 100-LQFP
  • CY37064P100-125AXI 100-LQFP
  • CY37064P100-125AXI 100-LQFP
CY37064P100-125AXI 100-LQFP
CY37064P100-125AXI 100-LQFP
CY37064P100-125AXI 100-LQFP
CY37064P100-125AXI 100-LQFP
CY37064P100-125AXI 100-LQFP

CY37064P100-125AXI

This CPLD has 2K gates and 64 macro cells, with a maximum operating frequency of 125MHz

在庫:9,906

  • 90日間のアフター保証
  • 365日の品質保証
  • 正規品保証
  • 7*24時間サービス検疫

迅速な見積もり

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概要 CY37064P100-125AXI

The Infineon Technologies' CY37064P100-125AXI is an integrated circuit (IC) from the Ultra37,000 series. It is a Complex Programmable Logic Device (CPLD) designed for embedded applications requiring high-speed and low-power consumption. This 10ns, 100-pin TQFP CPLD features 64 macrocells and 69 I/O pins, making it suitable for various industries such as industrial control, medical devices, and automotive electronics. With an operating temperature range of -40°C to 85°C, the CY37064P100-125AXI is reliable in a broad range of environments. The device can be programmed in-system using Infineon's proprietary programming method. It also features a delay time of 10ns (tpd), making it suitable for high-speed applications.

CY37064P100-125AXI

主な特長

  • In-System Reprogrammable™ (ISR™) CMOS CPLDs
  • — JTAG interface for reconfigurability
  • — Design changes do not cause pinout changes
  • — Design changes do not cause timing changes
  • High density
  • — 32 to 512 macrocells
  • — 32 to 264 I/O pins
  • — Five dedicated inputs including four clock pins
  • Simple timing model
  • — No fanout delays
  • — No expander delays
  • — No dedicated vs. I/O pin delays
  • — No additional delay through PIM
  • — No penalty for using full 16 product terms
  • — No delay for steering or sharing product terms
  • 3.3V and 5V versions
  • PCI-compatible[1]
  • Programmable bus-hold capabilities on all I/Os
  • Intelligent product term allocator provides:
  • — 0 to 16 product terms to any macrocell
  • — Product term steering onan individual basis
  • — Product term sharing among local macrocells
  • Flexible clocking
  • — Four synchronous clocks per device
  • — Product term clocking
  • — Clock polarity control per logic block
  • Consistent package/pinout offering across all densities
  • — Simplifies design migration
  • — Same pinout for 3.3V and 5.0V devices
  • Packages
  • — 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages
  • — Lead(Pb)-free packages available
CY37064P100-125AXI

応用

  • Industrial control systems
  • Medical devices and equipment
  • Automotive electronics and infotainment systems
  • Aerospace and defense applications
  • Consumer appliances and smart home devices
CY37064P100-125AXI

仕様

以下は、選択された部品の特性やカテゴリーに関する基本的なパラメータである。

Series Ultra37000™ Package Tray
Product Status Obsolete Programmabe Verified
Programmable Type In-System Reprogrammable™ (ISR™) Flash Delay Time tpd(1) Max 10 ns
Voltage Supply - Internal 4.5V ~ 5.5V Number of Macrocells 64
Number of I/O 69 Operating Temperature -40°C ~ 85°C (TA)
Mounting Type Surface Mount Package / Case 100-LQFP
Supplier Device Package 100-TQFP (14x14) Base Product Number CY37064

保証と返品

保証、返品、および追加情報

  • QAと返品ポリシー ?

    部品の品質保証: 365 日

    返品・返金:90日以内

    返品・交換:90日以内

  • 配送と梱包 ?

    配送: たとえば、FedEx、JP、UPS、DHL、SAGAWA、YTC など。

    部品パッケージ保証: 100% ESD 帯電防止機能を備えた当社のパッケージは、高い強度と優れた緩衝機能を備えています。

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packageimg

CY37064P100-125AXI

This CPLD has 2K gates and 64 macro cells, with a maximum operating frequency of 125MHz

在庫:

9,906